The invention relates to a bistable flip-flop with a first inverter stage driven by an input signal and capable of being switched into a disabling state by a clock signal, with a second inverter stage which is driven by the clock signal and which can be switched into a disabling state by an output signal of the first inverter stage, and with a third inverter stage which is driven by an output signal of the second inverter stage and which can be switched into a disabling state by the clock signal.
A bistable flip-flop of this kind is known from the published proceedings of the "IEEE 1993--Custom Integrated Circuits Conference", pp. 27.6.1-27.6.4. The bistable flip-flop designated there as dynamic flip-flop has three inverter stages of which the first is triggered by an input signal, the second by a clock signal, and the third by an output signal from the second inverter stage. The first inverter stage can be switched here into a disabling state by a high level of the input signal, the second inverter stage by a low level of the output stage of the first inverter stage, and the third inverter stage by a low level of the clock signal. In this disabling state, the signal levels are temporarily stored at the outputs of the respective inverter stage. The result, an output signal corresponding to the inverted input signal and with signal edges synchronized to the clock signal, is obtained at the output of the third inverter stage.
The main disadvantage of this known flip-flop is that it cannot be put into a defined state independently of the input signal, i.e., the signal level at the output of the third inverter stage cannot be preset independently of the input signal.